资源列表
PS2_verilog_source
- 在vhdl开发环境下，关于协议PS2 verilog 源码
TOP_DATE
- Code to have an incremante date
bujindianjidingweikongzi
- 设计一个基于FPGA的四相步进电机定位控制系统。步进电机是利用数字信号控制的电机装置，步进电机每次接受到一组脉冲数字信号，便旋转一个角度，称为步进角。不同规格的步进电机的步进角不同，与电机内部的线圈数量有关。线圈中的供应电流决定线圈所产生的磁场方向-FPGA-based design of a four-phase stepper motor positioning control system. Stepper motor control using digital signal of the
VHDL06
- 16×4bit的FIFO设计代码，学习代码，请在下载24小时后删除。-16 × 4bit the FIFO design code, learning the code, please delete after 24 hours to download.
count64
- 将5MHz时钟信号分频后得到1.6/3.2秒可选的同步信号，还可接外接同步信号对其进行强制同步-To 5MHz frequency clock signal 1.6/3.2 seconds after the optional sync signal, external sync signal can then be forced synchronization
4_bit_parallel_add-sub
- 4 bit parallel add-sub with test bench.. in vhdl-4 bit parallel add-sub with test bench.. in vhdl..
encoder
- here aach ed h e sh if\er m\odupl€ e
CLK_DIV_N
- 对输入的时钟进行分频输出:输出频率＝ 输入频率/(2*N+2-Of the input clock frequency output: Output frequency = Input frequency/(2* N+2
12
- cordic algorithm using verilog code
motor-control
- 可逆计数器，有多重用途，可独立应用，亦可作为系统的一个模块！使用方便，-cycle count
PULSE_CDC
- Clock Domain Crossing (SLOW-to-FAST OR FAST-to-SLOW). This module transfers pulse IN clock domain to OUT clock -Clock Domain Crossing (SLOW-to-FAST OR FAST-to-SLOW). This module transfers pulse IN clock domain to OUT clock