资源列表
dds
- 基于FPGA的直接数字频率合成器(DDS)的设计-FPGA-based direct digital frequency synthesizer (DDS) design of
traffic1
- 只有代码/* 信号定义与说明: CLK: 为同步时钟; EN: 使能信号,为1 的话,则控制器开始工作; LAMPA: 控制A 方向四盏灯的亮灭;其中,LAMPA0~LAMPA3,分别控制A 方向的 左拐灯、绿灯、黄灯和红灯; LAMPB: 控制B 方向四盏灯的亮灭;其中,LAMPB0 ~ LAMPB3,分别控制B 方向的 左拐灯、绿灯、黄灯和红灯; ACOUNT: 用于A 方向灯的时间显示,8 位,可驱动两个数码管; BCOUNT: 用于B 方向灯的时间显示,8
Bin16_BCD5
- it is a binary16 to BCD converter .it will work on spartan 3 xilini devices.
statemachine
- 一个用vhdl语言写的交通灯控制的例子,可以很好的学习vhdl语言中状态机的使用。-Written in a language with vhdl traffic light control case study can be a good vhdl state machine language to use.
key1
- 矩阵键盘实验1:向用户介绍矩阵键盘扫描实现的方法,没有考虑去抖和判断键弹起的问题;把相应的键值显示在数码管上-Matrix Keyboard Lab 1: Introduction to the user to achieve the keyboard scan matrix approach, not considered to shake and bounce to determine key issues the corresponding keys on the display in
jiaotongdeng
- 交通灯,红黄绿黄依次亮,黄灯亮的时间相对较短,红绿灯亮的时间一样-Traffic lights, red yellow and green turn yellow light, yellow light of the relatively short time, the same time, bright lights
shift_1d_16
- truncation using vhdl
1
- 信号发生器VHDL实现,实现一种信号的产生-Signal generator VHDL implementation to achieve produce a signal
uart_rx
- UART 接收模块,UART底层模块,实现各种波特率的uart接收-UART receive module,complete all Baud rate transfer receive。
hw2_final
- 讓LCD聖誕樹有變化,包括彩帶及移出螢幕等等。-Make xmas tree be displayed on LCD screen.
ads1252
- 用fpga控制ads1252采样,晶振高,速度快,采用的是同步模式,采样回来的前5个值不准,取值要从第6个值开始,第一位是标志位-With fpga control ads1252 sampling, crystal, high speed, using the synchronous mode, the first five sampling returned values are not allowed, ranging from the first six va
generate-coordinates
- 使用VHDL编写语言,巧妙的利用计数器和循环输出一个坐标系,由于VHDL出现负数比较麻烦,全部由正数代替,输出一个原点在中心,半径128的256×256的坐标。方便坐标变换以及用此坐标做算法。-Use of VHDL language, clever use of counter and loop outputs a coordinate system, because VHDL negative too much trouble, all replaced by a positive numb