资源列表
mymul
- 这是一段用VHDL语言编写的程序 用FPGA实现模糊控制器
874245
- 用vhdl语言编写设计8位總線收發器，很不错，大家快下啊-VHDL design language with eight bus transceiver, is pretty good, we soon ah
square_root
- /* root_x is an 8 bit number with four bits in front of the binary point and four bits behind, increment is an 11 bit number with 3 bits in front of the binary point and 8 bits behind the binary point. In order increase resolution and preve
alu32
- 32 bit ALU design using VHDL code for Xilinx ISE Foundation
New-folder
- VHDL code for ring and other counters
testbenchHw9-Parts-Mem
- // EE 361 Hw 9 Testbench for sequential circuit Parts // * 128 word data memory and IO
mfsk
- MFSK的verilog HDL程序，程序简单，易懂-The MFSK The verilog HDL program
CRC.vhd
- CRC 8bit for bus monitor
1122334455
- 设计一个十进制计数器，具有显示位置随计数时钟在八个数码管中左右滚动的功能-Design of a decimal counter, a display position with the count clock in eight digital tube rolling around functions
spi
- SPI 从机verilog设计,验证通过！-SPI interface slave verilog
D_A_CONTROLER
- AD5546芯片的控制逻辑，只需送入待转换量，该模块即可完成对芯片的写入等功能。-AD5546 chip control logic, simply amount to be converted into the chip module to complete the write functions.
COMB
- We use port map statement to achieve the structural model (components instantiations). The following example shows how to write the program to incorporate multiple components in the design of a more complex circuit. In order to simulate the design, a