资源列表
signal-generator
- FPGA 信号发生器的程序，在实验板上调试成功
shift_register
- -- DEscr iptION : Shift register -- Type : univ -- Width : 4 -- Shift direction: right/left (right active high) -- -- CLK active : high -- CLR active : high -- CLR type : synchronous -- SET active : high -- SET type : synchronous
trafficlight
- design and simulate the traffic light controller-design and simulate the traffic light controller
RGB_YCrCb_Multiplierless_Color_Converter
- verilog source code for RGB YCrCb color converter
max7000vgasync
- VHDL animation with simple codes
ad0809verilog
- 这是用Verilog编写的ad0809，和之前的vhdl功能相似，不过开发环境部一样-It is written in Verilog ad0809, and before the vhdl function similar, but the Ministry of Environment as the development
ram_dp_sr_sw[1]
- dual port ram control-dual port ram control dual port ram control dual port ram control
sram_duxie
- 用FPGA控制的SRAM读写程序，要写的数据是由FPGA内部寄存器产生-Control with FPGA SRAM read and write procedures
ps2
- verilog写的v5板子ps2测试程序，已测试 可以直接使用-this is a code applied for ps2 in v5
descr_20
- 完成20位并行数据的伪随机序列解码，配合扰码部分，提高数字信道的SNR。已经通过综合仿真，并正在具体项目中运行，未发现任何缺点。-Completion of the 20 pseudo-random sequence of parallel data decoding, with part of the scrambling code, and to improve the SNR of the digital channel. Through integrated simulation, an
DENGIAOTHONG
- Traffic lights, there are two operating modes
keydou
- VHDL语言编写按键区抖动的代码，但是很差劲的蓝马-VHDL language the keypad code jitter, but very bad at the Blue Horse