资源列表
dff
- 用VHDL语言编写的带进位、置位、复位的D触发器，异步清零D触发器，同步清零D触发器-library ieee use ieee.std_logic_1164.all use ieee.std_logic_unsigned.all entity exp7_10 is port( clk: in std_logic d: in std_logic clr: in std_logic en,s:in std_logic q: o
SOU
- 这是用C写的正弦函数定点数据生成代码，内容是生成verilog中RAM或者ROM和Matlab处理时的所用的数据。-It is written with C fixed-point data generate code sine function, the content is generated verilog RAM or ROM, and Matlab in the processing of the data used.
bt1120p_gen
- bt1120时序生成，verilog程序，1920x1080p60分辨率-synchronized video timing generation itu bt1120 within verilog program, 1920x1080p60 resolution
code
- 7位表决器，实现投票选择结果呈现； 减法器编码。-7 bit voting machine, realize the voting choice results present the encoding.
pcreg
- pc寄存器，上升沿为寄存器赋值，随时读出寄存器内部的值。-pc register, rising to register assignments, ready to read the internal register values.
LED-light
- 流水灯控制程序，用于控制LED灯的闪烁，调试通过的，用于FPGA开发-Water lamp control procedures for the control of LED lights flashing, debugging through the use of FPGA development
mimo.matlab
- 仿真mimo的matlab代码，网上找的，个人感觉很有用。请大家支持-failed to translate
bit_logic_ulogic
- truong trinh thuc hien viec chuyen doi cac kieu du lieu
TCDTiming
- tcd1501d 时序，用于tcd1501d的驱动，不知可否好使，希望供大家参考-the code is for tcd1501d ccd timing，wish it is useful for you
s_p2m_onechnl
- 这是一个串转并的代码示例，将串行的数据转换为并行数据-This code example, a string transfer and the serial data is converted to parallel data
traffic
- verilog,使用两个传感器的铁路道口异步交通灯设计。-an asynchronous circuit that is to control the gates and red flashing light at a railway level crossing
esjz
- 60-24 模拟时钟分钟小时计数器。 分钟为60标号的计数器从0-1-2-……58-59 循环往复，完成1个分循环，小时循环计数器加1；小时采用24小时制。-60-24 simulator of a clock, 60 is for minutes, starts 0 increased by 1,and cycle period is 60 once a cycle is finished, the 24 adding-type counter will increase by1 and