资源列表
树式除法型开方器VERILOG实现
- 树式除法型开方器VERILOG实现,用于任意长度的无符号数的开方运算,Square root of the tree-type divider-type device to achieve VERILOG
DG408
- FPGA对模拟开关DG408的控制程序，实现不同需求的情况下，模拟通道的转化。-FPGA on the DG408 analog switch control procedures, to achieve the different needs of the circumstances, the conversion of analog channels.
softdrink
- 自动售货机实现，采用VERILOG语言编写源码，与大家分享，共大家参考-Vending machine implementation, the use of language VERILOG source to share with you a total of U.S. reference
clk_div
- deviseur de fréquence pour fpga
adc_cvt
- FPGA控制AD采样一个周期采样32点，求给改成64点-FPGA controls the sampling period 32 AD sampling a point, seeking to change the 64-point
half_adder
- 半加器 用verilog语言编写一个半加器，测试结果正确。-half adder
code
- 五人表决器,设计一个五人表决器，掌握异步清零以及锁存器的工作机制-Five people voting, voting machine design a five master asynchronous clear and latch mechanism
VHDL 1602
- VHDL的1602代码，基于FPGA的1602液晶代码
jiecheng
- 利用Verilog语言中的函数调用实现阶乘运算的功能-Function calls use Verilog language implementation of the factorial function computing
qam1
- vhdl code for adde-vhdl code for adderrrrrrrrrrrrrrrrrrrr
1
- 基于51单片机的数字频率计+1602显示-Based on 51 single-chip digital frequency counter 1602 shows
DVF16
- 16位分频器的设计编程源代码 使用QuartusⅡ进行编程和调试-16 divider programming source code for programming and debugging using the Quartus II