资源列表
ad
- STC12C5A60S2的AD转换，并送入LCD显示-STC12C5A60S2 the AD converter, and into the LCD display
frequency_divider
- 分频器的编程思路为：32MHZ经过第1次分频变成1KHZ，再经过第2次分频变成100HZ，分别输出两次分频结果。-Divider of programming ideas for: 32MHZ after the first band to become a sub-sub-1KHZ, and then after the 2nd sub-band into a 100HZ, respectively, the results of the output frequency of the two
xianshi_hs
- 用调用函数的方式编写的共阳数码管16进制显示的程序。可方便扩展显示位数。-Call the function with the way Yang prepared a total of 16 hexadecimal display of digital control procedures. Can be easily extended display digits.
PLL
- 基于FPGa实现一个数字锁相环，实现时钟恢复，具有较好的通用性。-pll
abel
- 光栅尺辨向四分频ABEL代码,能够实现普通光栅尺的辨向以及脉冲细分，输出有四路信号-Identified to the quarter-frequency grating ruler ABEL code, and be able to achieve common Grating identified, as well as pulse segments to the output four-channel signal
unicntr
- 通用寄存器，可以双向计数存储，模式通过三位比特数据进行控制-General registers, can be bi-directional counting storage, mode of data through the three-bit control
dll
- 在传输数字信号的时候，需要时钟定时，本程序可以从数据中恢复出时钟-In the transmission of digital signals, the need for clock timing, the program can recover a clock from the data
3-vhdl
- VHDL实验 4位可逆计数器的设计与实现-4 reversible counter
led_controller_register
- 使用VeirlogHDL实现的一个LED数码管控制器-A LED controller implemented with VerilogHDL program langrage
mul
- 使用Verilog实现的原码4位数的移位乘法器-Using Verilog to realize the original code 4 bit shift multiplier
clk_div
- Clock divider in VHDL.
ASK_two
- 幅度键控调制是数字调制中 最为基本调制方式之一，这里的 文件是幅度键控调制的FPGA Verilog 文件-Amplitude shift keying modulation is one of the most basic digital modulation modulation, where the file is amplitude shift keying modulation FPGA Verilog file