资源列表
choosebcd
- 48位BCD码自动识别，并判断是否有无用位，并输出到下一段输出-48 BCD code automatic identification and to determine whether any use of digital and output to the next section of the output
PWM
- PIC16F877A 软件件产生PWM，适合PIC初学者-failed to translate
control
- alu code for pipeline processor
counterms
- verilog语言写的可置数的倒计时计数器，共四位bcd码，分别为分钟两位和秒两位。波形完美无毛刺.开发环境没找到verilog只好写了vhdl-verilog based counter for minutes and seconds
mux2to1
- 2路选择器，基于VHDL语言，在epm570板上的开发程序-2-way selector, based on VHDL, epm570 board development process.
aqusition
- 此程序用于视频采集过程中CPLD对时序的转换与组合代码，每两行采集一行，两列采集一列，减小数据量，同时能保证采集完整的一幅图像（输出OUT用于DSP或者单片机中断）
eff1
- 利用Verilog实现的跑马灯，从护栏管的一端循环到另一端。其他类似此类的循环语句基本一样。-Marquee achieved using Verilog, from one end of tube to the other end of the cycle. Other similar expressions of such basic, like the cycle.
f_h_v
- this file describe how to recupere the signals from a video signal when it out from an ADV7180 chip.
key
- 矩阵键盘扫描程序，通过行扫描和列扫描确定按键位置。-Matrix keyboard scanner，Key position determined by line scan and column scanning.
COUNT60
- 这是一个用VHDL语言编写的60进制秒计数器。欢迎下载。-This is a VHDL language with 60 decimal seconds counter. Welcome to download.
dfghg
- 带同步复位的状态机！可用于了解状态机的编程原理和格式，还有同步复位的实现！-With synchronous reset the state machine! State machine can be used to understand the principles of programming and formats, as well as the realization of synchronous reset!
fifo_sync
- A Synchronous FIFO Design