资源列表
madeng
- 硬件描述语言VHDL的跑马灯程序,对于初学者有一定的借鉴.-Hardware Descr iption Language VHDL of the Marquee procedures have some reference for beginners.
Sobel
- Verilog code to calculate Sobel
zhuantaiji
- 简单的状态机设计，功能是检测一个5位二进制序列“10010”。考虑到序列重叠的可能，有限状态机共提供8个状态（包括初始状态IDLE）。-Simple state machine design, function is to detect a 5-bit binary sequence " 10010." Taking into account the possibility of overlapping sequences, finite state machines prov
counter
- N-bit binary counter using behavioral model
Cpulib
- tarahie alu ba estefade az codhaye ketabe mano be zabune vhdl
rom_con_aa
- VERILOG 多线程控制程序，实现状态机控制ad采集-VERILOG multi-threaded control program, to achieve a state machine control ad acquisition
dds
- 数字频率合成器，生成所需频率的正弦波和余弦波-Digital frequency synthesizer to generate the desired frequency sine wave and cosine wave
key_scan
- 按键消抖！verilog版本的，延时程序，已经过测试-Key debounce verilog version, the delay procedure has been tested
GrayCounter2
- gray counter for async FIFO design
butt_dit_r2
- buuterfly Radix 2 FFT
Projects
- this is sub and adder in vhdl &writed in ISE
AES Algorithm
- The source codes describes the AES Algorithm