资源列表
SingleclocksynchronousdesignmetricCNTR
- 用VHDL 设计的单时钟同步十进制可逆计数器的设计-VHDL design using a single clock synchronization decimal CNTR Design
mux2_1
- 2选1数据选择器，用于数据的切换，vhdl编写，实际使用过-mux2 to 1
4ask
- 数字通信系统4进制振幅键控4ASK信号的调制的VHDL代码-Digital Communication Systems 4 binary amplitude shift keying modulation 4ASK signal VHDL code
screen_1
- 符合avalon总线接口的LED控制软核-Avalon bus interface LED control soft-core
wsm
- 八位数码管的位扫描程序，已在开发板上验证使用-Digital tube scanner, has been verified on the development board to use
counter8
- 8 位 计数器，带使能键和重置键。附带testbench, verilog 环境-8 bit counter
22_deadlock
- 用vhdl编写的加法程序，很好，很实用，适用于初学者-Vhdl adder with the preparation of procedures, very good, very useful for beginners
comparator
- this is a souce code for comparator
drink-machine
- Verilog codes for drink machine design project codes
VHDL
- 基于VHDL语言和CPLD开发板的，分频电路电路的开发。-Based on VHDL and CPLD development board, divider circuit circuit development.
cell_arch
- cell architecture for dual port ram
triangle
- 这是用vhdl编写的三角波产生程序，比较简单，但是对于开发学者的思维还是有帮助的。当时我受益颇多，拿出分享。-This is a program used to generate the triangular wave vhdl written, relatively simple, but for the development of academic thinking is helpful. At that time, I benefited a lot, come to share.