资源列表
Counter8
- Counter 8 bits Vhdl Code
adder16.v
- 这是自己写的16bit ripple 形式的加法器的代码，用verilog写的，如果有用，fell free to download-This is to write 16bit ripple adder form of code, verilog written, if useful, fell free to download
decoder
- 三八译码器，可以通过三位输入实现八位的输出，可连接FPGA下板。-Thirty-eight decoder output can be achieved through three eight inputs can be connected to the lower plate FPGA.
divider1-(3)
- Code for divider is written in Verilog where divider and dividend both are of 8 bits. Division is done using continuous subtraction method until the divisor becomes greater or equal to dividend.
alu_wide2
- Generating a wider ALU from two small ones
szdyb
- 基于Verilog HDL的数字电压表的程序-Verilog HDL-based procedures for the digital voltmeter
2-Decimal-BCD-Decoder
- 二-十进制BCD译码器，就是用VDHL编写的将二进制转化为十进制的BCD译码器-2- Decimal BCD Decoder, is to use VDHL written into the binary decimal BCD decoder
4_COMP
- ＣＰＵ内部的比较器用ｖｈｄｌ语言在可编程逻辑器件上的实现-The comparison of the CPU internal used VHDL language in programmable logic devices for fulfillment
adder4
- 基于VHDL的4位加法器。 由4个一位全加器级联构成。-VHDL-based 4-bit adder. One consists of four full adder cascade.
comparator
- 32bit comparator code vhdl from an old project
anjian
- 按键按下一般会产生抖动现象，工程必须掌握消抖的方法，此程序可以实现按键消抖。-Keys away shaking
qdjs
- 10s倒计时，在复位高电平期间，开始倒计时，有某信号(抢答信号)输入，则恢复到10s并保持，准备下次计时。-10s countdown, at a high level during reset and start the countdown, there is a signal (answer signal) input, then back to the 10s and remains ready for the next timing.