资源列表
alu
- 加法器FPGA 实现，精简，快速，高效，有仿真文件-adder base on FPGA ，verilog HDL
Traffic_Light_Controller_Test_Bench
- VHDL Test Bench For Traffic Light Controller
Octal-D-Type-Register
- Octal D-Type Register with 3-State Outputs -- Simple model of an Octal D-type register with three-state outputs using two concurrent statements.
74ls47
- 74ls47原理，针对共阴型数码管，代码简短，可供参考-74ls47 schematic
15
- 一个15人表决电路，参加表决者为15人，同意为1，不同意为0，同意者过半则表决通过，绿指示灯亮，表决不通过则红指示灯亮。数码管显示赞成人数。-A 15-person voting circuit, voting for the 15 people who agree to 1, does not agree to 0, the consent of more than half the vote, the green indicator light, a vote is not passed t
jiajian
- 在QuARRTER 2环境里运行，实现选择性加减技术的功能，硬件描述语言。-In QuARRTER 2 environment to run, to achieve selective addition and subtraction techniques, hardware descr iption language.
ddc8chou
- 8倍抽取的DDC模块。verilog写的，调试通过-failed to translate
GCD_Control
- GCD控制器，该模块功能比较简单，适合初学者。易扩充。-GCD controller, the module is relatively simple for beginners. Easy to expand.
traffic_control_tb
- traffic controller verilog test bench code 2
ANTIREBOTE
- Codigo antirebote para utilizar en tu proyecto de digitales
AD9222_SPI
- AD9222模拟数字转换芯片串行口配置代码-Analog-digital converter chip AD9222 serial port configuration code
Mux4
- This Mux4 verilog code.-This is Mux4 verilog code.