资源列表
RAMexio
- verilog 语言的，PWM测试 梯形图速度控制程序新鲜的-verilog language, PWM speed control test procedures fresh Ladder
quanzixongxiyiji-verilod
- 根据日常生活中的洗衣机使用流程设计状态。 空闲——加水——洗涤——排水——加水——清洗排水——甩干——报警 - according to the processes and the use of washing machine in the daily life of the design state. Idle-------- washing water drainage water------ alarm dry cleaning and drainage
Control-of-small-lights
- 一个实用的用VHDL实现控制小灯的程序，可改变小灯闪烁的频率-A practical small lamp with VHDL control program to control the frequency of small lights flashing
Ram_test
- SRAM IS61LV64读写 经检验ok下载板子成功读写-SRAM IS61LV64 reader board successfully been tested ok download reader
CRC
- 在数据通信过程中，数据校验是必不可少的部分，CRC校验是一种高效的检验方式。-In the process of data communication,data verification is an indispensable part, CRC verification is an efficient way to test.
counterjhiuynjf
- 很不错的交通灯 很不错哦 大家一起下载 -quite the traffic lights is pretty good, oh everyone Download
topsequence
- modeling of fsm in vhdl
12
- 4位除法器 library IEEE use IEEE.std_logic_1164.all use IEEE.std_logic_unsigned.all entity fpdiv is port ( DIVz: out STD_LOGIC A: in STD_LOGIC_VECTOR (3 downto 0) B: in STD_LOGIC_VECTOR (3 downto 0) data_out: out STD_LO
jiafaqi
- 数字系统设计及VHDL实践半加器与全加器源代码-half-adder and full-adder
COUNT60
- 这是一个用VHDL语言编写的60进制秒计数器。欢迎下载。-This is a VHDL language with 60 decimal seconds counter. Welcome to download.
dfghg
- 带同步复位的状态机！可用于了解状态机的编程原理和格式，还有同步复位的实现！-With synchronous reset the state machine! State machine can be used to understand the principles of programming and formats, as well as the realization of synchronous reset!
fifo_sync
- A Synchronous FIFO Design