资源列表
lcd
- lcd屏幕的驱动开发，带偏移，带屏蔽功能显示。(LCD screen driver development, with offset, with screen function display.)
axi_slave
- amba总线中axi的slave部分，用verilog实现的slave.(The slave part of Axi in the AMBA bus, slave. implemented with Verilog)
374566d
- html documents for programming
372468a
- fpga documentation regarding something
371231d
- file information such as datasheet
lab2B(4)LFSR
- 实现4位二进制随机数的产生的verilog代码(Implementation of generation random 4 bits code in verilog)
A4_Clock
- 基于Altera的Cyclone4的时钟程序(clock program based on Cyclone4 of Altera)
uut_3
- VHDL设计的FIFO 经典结构 功能详尽 敬请参阅(VHDL designed FIFO classic structure functions in detail please refer to)
cnt8updown
- 8位上下同步计数器 适宜小型练手操作 易于理解(an 8-bit up and down synchronous counter in VHDL with the following features: (1) The same ports are used for signals to be inputted and outputted. The ports are bi-directionally buffered (three-state). (2) The counter is
2_4decoder
- 三种描述风格的VHDL代码，快速建立不同风格描述语言的概念及结构(Three styles of VHDL code to quickly establish the concept and structure of different style descr iption languages)
tt
- VHDL Implementation of decade counter
State_machine_1
- VHdL code to implement simple state machine