资源列表
counter_verilog
- DE2_70_D5M_LTM_sobel_dilation
Altshift_tabs_lab0
- programme en vhdl sur fpga
DE2_70 sobel
- DE2_70 sobel_dilationdsd
DE2_70_D5M_LTM_sobel_dilation
- DE2_70_D5M_LTM_sobel_dilation
DE2_70_D5M_LTM
- filtre de sobel sur fpga
Minor-1
- code for "booth multiplier" using verilog
major1
- code for inverting an image in verilog
major_brightness
- code to perform brightness operation
major_threshold
- code to perform thresholding operation on a picture
major1_contrast
- code to enhance a picture in verilog.
cpu_uart_leds_ip
- 基于Altera 的一个IP核，能完成串口收发,以及自定义IP,可以作为自定义AXI总线接口的例子(Based on Altera's IP core, to complete the serial transceiver, as well as custom IP, as a custom AXI bus interface example)
MAC网络控制的物理层控制程(VHDL)
- MAC网络控制的物理层控制程(VHDL)(The physical layer control of MAC network control (VHDL))