资源列表
Fpga-based-ADC-sampling-voltage-
- 基于fpga的ADC采样电压用，显示在数码管上。verilog语言。-Fpga-based ADC sampling voltage used, displayed on the digital pipe. verilog language.
dsp_core_tx_filter
- 应用在USRP N210上的XIlinx的FPGA开发板上面的变采样滤波器，实现25--30.72M的变采样滤波器，适应LTE物理层的要求-Application on the USRP N210 FPGA development board above XIlinx variable sampling filter, to achieve 25- 30.72M variable sampling filter, adapt LTE physical layer requirements
Cyclone4_SD_Card_Audio_Player
- 基于cyclone4 FPGA芯片的音频播放器完成项目工程，包括SOPC项目代码，以及SD卡读取模块Verilog IP，以及完整的Q2下项目工程。-Cyclone4 FPGA chip based audio player to complete the project works, including the SOPC project code, and SD card reader module IP, as well as complete Q2 next project.
tongxin485
- 关于Verilog语言学习-485通信程序-Verilog on language learning-485 communication program
TLV-5626
- DA转换芯片TLV5626的驱动程序，调试通过-DA zhuanhuanxinpian TLV5626 dequdongchengxu ,tiaoshitongguo
pingball
- 用verilog写得弹珠小游戏，在BASYS平台上运行的-Pinball game with verilog written, running on a platform in BASYS
ddr3_mcb1
- 基于SPARTAN 6 的DDR3的实现。-The Verilog code for DDR3 on the SPARTAN 6
man2uart_latest.tar
- fpga uart串口ip核，源代码例程。-fpga uart ip core
LabA1Design2
- 设计模式比较器电路：电路的输入为两个8位无符号二进制数a、b和一个模式控制信号m；电路的输出为8位无符号二进制数y。当m=0时，y=MAX(a,b) 而当m=1时，则y=MIN(a,b)。要求用多层次结构设计电路，即调用数据选择器和比较器等基本模块来设计电路。-Design pattern comparator circuit: circuit input as two 8-bit unsigned binary numbers a, b and a mode control signal m
LabA1Design1
- 设计求两数之差的绝对值电路：电路输入aIn、bIn为4位无符号二进制数，电路输出out为两数之差的绝对值，即out=|aIn-bIn|。要求用多层次结构设计电路，即调用数据选择器、加法器和比较器等基本模块来设计电路。-Design for the number two absolute value of the difference between circuits: circuit input aIn, bIn a 4-bit unsigned binary number, the circu
crc32
- 循环冗余校验码，CRC32算法的Verilog代码-Cyclic redundancy check code, CRC32 algorithm Verilog code
ADS7816
- verilog ADS7816采集程序，-ADS7816 verilog