资源列表
clk_DCM_50to75MHz
- 调用ISE010.1的IP核DCM来实现频率倍增，本程序实现的是50MHz到75MHz的倍增，开发者可以根据DCM的参数设置实现不同频率的倍增-Call ISE010.1 IP core DCM to achieve frequency doubling, the program is 50MHz to 75MHz multiplication, developers can implement different parameter settings of DCM frequency mult
chengfaleijia
- verilog 乘法累加器 包括工程项目及仿真波形图-verilog multiplier-accumulator including the project and the simulation waveform
signed_integer_divider_latest.tar
- VERILOG IMPLEMENTATION OF SIGNED INTEGER DIVIDER
spramipcore
- 使用vhdl语言在fpga环境下实现ip core spram-Environment in fpga vhdl language used to achieve ip core spram
chengfaqi
- 基于fpga的乘法器设计 已经验证请放心下载-Fpga-based multiplier design has been verified, please rest assured download
fpga
- FPGA控制DS18B20温度测量及显示,温度范围-20℃至100℃，精度0.1℃。数据刷新周期小于1秒。产生警报 -FPGA control DS18B20 temperature measurement and display
new-project
- 基于verilog的贪吃蛇 苹果同屏幕同时出现，贪吃蛇吃完所有苹果游戏结束，贪吃蛇的另一种写法-Based on the same screen verilog Snake Apple simultaneously, Snake eating all the apples end of the game, Snake' s another way
PWM
- 程序PWM_rate1可以输出占空比可调的方波，并把占空比用数码管显示出来。-verilog pwm
8b10b
- 8b10b编解码，用于光通信和千兆以太网，verilog编写，已验证-8b10b codec for optical communications and Gigabit Ethernet, verilog prepared Verified
UART_RX
- 232串口源程序 verilog实现，频率可调 接受部分-RS232 verilog
ads1252
- 用fpga控制ads1252采样，晶振高，速度快，采用的是同步模式，采样回来的前5个值不准，取值要从第6个值开始，第一位是标志位-With fpga control ads1252 sampling, crystal, high speed, using the synchronous mode, the first five sampling returned values are not allowed, ranging from the first six va
mux16
- 十六位乘法器的verilog hdl 实现 及 modelsim 仿真 环境为quartusii9.0 自动调用modelsim 6.5输出仿真结果-fpga verilog hdl modelsim quartusii 16-bit multiplier