资源列表
zs
- 基于fpga的数字频率计，verilog编写，可修改闸门宽度0.1s/1s/10s，可测频率1hz~1mhz，包含整个工程，内部分频模块为了仿真方便改小了，后面注释为50mhz晶振下的分频值，可根据需要自行修改-Fpga-based digital frequency meter, verilog prepared to modify the gate width 0.1s/1s/10s, measurable frequency 1hz ~ 1mhz, contains the entire
DDS
- DDS信号源实现源码，实现正弦波、方波、三角波等，频率、相位可调。-DDS signal source to achieve source
Cpld
- 本程序是用verilog语言在CPLD上实现智能小车控制部分，并通过并行通信，实现与单片机的通信。-This program is to control the robot car,and comunication with the C8051FXX by the Parallel communication.
pwm_led
- 基于FPGA的PWM控制LED灯的verilog程序源代码-FPGA-based PWM control of LED lights verilog source code
MOTION_DECT
- 在EP3C16 FPGA开发板上实现了对数字摄像头的数据采集，颜色空间变换并进行摄像头中的运动物体进行检测，并实时的显示在VGA显示器上。使用quartus 10.0打开，注意不要使用中文路径。-In EP3C16 FPGA development board to achieve the right digital camera for data acquisition, color space conversion and for the camera to detect moving ob
verilog-codes-for-booth2
- 由verilog编写的采用booth2编码的16*16乘法器-a 16*16 multiplier with booth2 coding by verilog
stopwatch-VHDL
- 自己用VHDL语言写的一个秒表程序，包括秒，分秒和百分秒。有程序说明和VHDL代码，一看就懂-Own use VHDL language used to write a stopwatch program, including the seconds, minutes and seconds and hundredths of a second. There descr iption of the procedures and VHDL code, one can understand
sgmii_latest[1].tar
- 这个工程应用于千兆网传输的物理代码子层，同时也用于SGMII接口。两者不同之处是自动协商时链接定时器和控制信息。-This core implements Physical Coding Sublayer of 1000BaseX transmission (IEEE 802.3 Clause36 and 37). This core can also be used for SGMII interface as this interface leverages 1000BaseX PCS.
Sdram_Control_8Port
- 用verilog写的8端口SDRAM模块-8-port SDRAM module
encoder104
- 独热码到二进制代码的转换即10输入4输出的二进制编码器的verilog程序。-One-hot code to binary code conversion, or 10 inputs 4 outputs the binary encoder verilog program.
Cont_THS1207
- FPGA控制THS1207多通道ADC的verilog源代码-FPGA control THS1207 multi-channel ADC' s verilog source code
AN66806
- 提供了利用 GPIF 对 FX2LP 与同步 FIFO CY7C4625-15AC 之间的接口进行设计的源代码-Provides for the use of GPIF FX2LP and synchronization FIFO CY7C4625-15AC to design the interface between the source code