资源列表
avs_aes_latest
- This is source code for something very important that is AVS AES standard hardware code for implementation both ASIC and FPGA
ODriveFPGA-master
- 使用FPGA控制永磁同步电机的代码,实现对永磁同步电机的控制功能。(Motor control by using FPGA)
signed_add
- 有符号定点数加法运算代码,使用Verilog HDL语言实现(Code writing in Verilog HDL,to solve the problem about signed number calculation.)
jiou
- 实现奇偶校验,根据波形仿真检测序列的奇偶(Implementing sequence parity check)
2015112208
- 实现8位二进制数的原码一位乘法,并将乘法运算结果通过七段数码管显示(The realization of the 8 bit binary code a multiplication)
EDAC
- Error Detection and Correction
DA_AD
- 基于FPGA的AD和DA设计代码及文档(Design code and document of AD and DA based on FPGA)
spi_sign_tap2
- 实现了SPI主设备的功能 CPOL=1 CPHA=1,同时包含了PRBS9的数据生成模块,也可以切换为发送固定的数(SPI MASTER CPOL=1 CPHA=1)
sata_opencore_rtl
- SATA控制器代码,来自opencore(code for SATA controller, from opencore)
ex22
- 一种用verilog在fpga上实现VGA显示驱动的方法(the vga display method of fpga with verilog.)
music
- implement a musis player
ve_lab
- verilog语言实现智能交通灯控制系统,除现有交通灯系统基本功能以外,还包括未来交通可能出现的一些需要智能控制的情况进行自定义规则(比如检测车流量来控制交通灯持续时间,高峰期主干道绿灯时间将加倍等规则)(The project was completed by myself about two months ago. I think it will be useful for traffic control system.But there are many points needed to