资源列表
LCD_Driver
- A project in VHDL for LCD - Driver-A project in VHDL for LCD- Driver
sumador
- sumer vhdl code for FPGA of Xilinx
crc
- 用verilog实现串进并出的CRC算法-Achieved with verilog into and out of the CRC series algorithm
ps2
- PS2断码和通码的16进制，供大家学习，共同提高，-PS2 break codes and pass codes 16 hex, for everybody to learn and improve together,
farrow
- 通信中常用的Farrow滤波器的Verilog实现-Communications of the Farrow filter used in the realization of the Verilog
alu
- alu for verilog it s simple
ALU
- vhdl code for alu and detemines the basic components of alu unit in cpu system
1bitAdder
- vhdl code for multiplication of two sign digit and every other 2 s complement numbers and every number in nega binary form
jitter_filter
- Verilog按键消抖程序，根据按键时间进行消抖-Verilog key debounce program, according to the key debounce time
cnt10
- 基于altera开发板的10进制显示程序，用于初学者-Altera development board based on 10 hexadecimal display program for beginners
fsk_two
- FSK是数字调制中最为常见的一种调制方式 Verilog 文件可以在FPGA上完成实现功能。-FSK is a digital modulation in the most common form of modulation can be done to achieve functional Verilog file on the FPGA.
mixer_tx
- Digital Mixer: 16-bit signed input with DDS