资源列表
8051
- VHDL语言编写的SW8051IP核，并加入ROM,RAM,RAMX,PLL模块，可下载HEX文件并验证成功-VHDL language SW8051IP nuclear and add ROM, RAM, RAMX, PLL modules, you can download the HEX file and verify success
tPad_VIP
- altera VIP的使用例子,使用SOPC-altera VIP use examle for tpad
08_ethernet_1g
- Artix7 XC7A100T芯片控制千兆PHY的二层通信，源代码(Artix7 XC7A100T chip control Gigabit PHY two layer communication, source code)
Flash
- （7）实验7：外部FLASH扩展实验，完整的设计工程文件在Flash文件夹下-(7) Experiment 7: the external FLASH expansion experiments complete design project files in the Flash file folder
VHDL
- VHDL（Very High Speed Integrated Circuit）教程!供VHDL初学者使用！-VHDL (Very High Speed Integrated Circuit) Tutorial! VHDL for beginners to use!
uart_test
- 收发端都采用2M波特率发送串口数据，通过PIN口直接输入输出串口数据，目的是为了跟外围高速器件完成高速的串口数据的收发，普通USB转串口的都只能支持不到1M的波特率，内部采用乒乓FIFO进行时钟域切换以及缓存(The transmitter and receiver are used 2M baud rate serial data transmission, directly through the PIN port serial input and output data, the purp
DE2_LCM_DISP_sucess
- 这是altera公司的DE2-35开发板下的一个液晶显示屏源程序代码工程，液晶显示屏是友晶公司的，包括液晶显示屏的驱动以及显示等模块有需要的人，可以下载 -Altera DE2-35 development board of the company, a liquid crystal display source code engineering, LCD display the Terasic, including LCD driver module and display needs,
DE2_SD_Card_Audio
- DE2_SD_Card_Audio程序,有简单的播放,快进,快退,随即循环顺序播放-DE2_SD_Card_Audio procedures, a simple play, fast forward, rewind, then loop order of play
SPI_TEST
- verilog SPI 读写时序，测试验证OK.-SPI Verilog Code, Master and Slaver.
clock_sel
- 无毛刺多时钟选择，可根据不同模式选择不同时钟(Multi clock selection, different modes can be selected according to different clock)
RCQ208_V3_24TFT
- Quartus NIOS例程，控制320*240TFT液晶显示，包括汉字、字符显示及显示缓存SDRAM控制驱动-Quartus NIOS routines, control 320* 240TFT LCD, including Chinese characters, character display and display control drive cache SDRAM
onchip_seg
- NIOS FPGA片上存储器的核12345673564-NIOS FPGA on-chip memory nuclear 12345673564