资源列表
ps
- vhdl code to change the bits stream from parallel to serial
multiplier
- 压缩的乘法器。是基于VERILOG 语言实现的，有较快的速度。-Compression of the multiplier. Is based on the VERILOG language, there is a faster speed.
dualport
- dual port sram test programe-sram test
cascaded-muliplier
- Verilog based for cascaded multiplier design-Verilog based for cascaded multiplier design
AntGlitch
- 运用VHDL语言，实现脉冲采集的滤波子程序，利用打两拍进行毛刺滤波，可以将该子模块加载到主程序中。-The use of the VHDL language, to achieve the the pulse collected filtering subroutine utilize playing two beats glitch filtering, the sub module is loaded into the main program.
median-filter
- 基于FPGA的图像中值滤波算法的优化及实现vhdl-中值滤波 利用VHDL语言实现三级流水线中值滤波-FPGA-based image filtering algorithm optimization and realization of vhdl-median filter using VHDL language three pipelined median filter
HDL
- 这是一个高手写的关于如何提高HDL的编程能力，很有好处的。-This is a master to write about how to improve the capacity of HDL programming, it is beneficial.
counter
- 这是一个计数器的代码，用vhdl编写，实现循环技术功能-this is a counter used to count numbers in vhdl
toplevel_png
- top level for ping pong game on vhdl
clk1hz
- 分频电路 将电路分频为1赫兹 可用于FPGA实验-Frequency divider circuit is a circuit that can be used in FPGA Hz
CRC32_D82
- CRC 校验 // polynomial: (0 1 4 5 7 8 10 11 12 16 18 22 23 26 32) // data width: 8 // convention: the first serial bit is D[7]- // polynomial: (0 1 4 5 7 8 10 11 12 16 18 22 23 26 32) // data width: 8 // convention: the first serial bit i
counter
- Ring Counter implemented in VHDL usign finite state machine design.