资源列表
NIOSII_LCD
- 基于FPGA的NIOSII ILI9320LCD的显示工程。-FPGA-based NIOSII ILI9320LCD display works.
2025L
- 2025驱动程序很好用的很难找的我们找了好久才找到的希望对大家有帮助-The 2025 driver good with hard to find we are looking for a long time to find the hope to help
PaintBrush
- To use the device port ISP1362 and NIOS II CPU for mouse movement detection and the VGA interface and implement a Paint Brush Application[1] using Cyclone II FPGA on the Altera DE2 board.
ICC_AVR
- 基于单片机的流水灯设计，实现led灯一次点亮-Based on MCU water lamp design, to achieve a LED lamp lit
《HELLO FPGA》- 软核演练篇
- FPGA实践分析 需要的详细介绍这些方面的知识(FPGA practice analysis requires detailed knowledge of these areas)
Nios_II_SPI
- 本源码为Nios II的开发示例,主要演示Nios II的SPI总线设计。开发环境QuartusII。 本示例十分经典，对基于SOPC开发的FPGA初学者有很大帮助。-The source code for the Nios II development of an example, the main demonstration Nios II design of the SPI bus. Development environment QuartusII. This example is
Nios_II_SPI
- 基于sopc的SPI例子学习资料，对于初学者来说很有帮助的。-Learning materials based on the SPI example sopc
NiosIISPI
- NiosII上spi总线的设计，源代码简洁易懂，有助于学习者读懂和移植-NiosII on spi bus design, source code easier to understand, to help learners understand and transplantation
sgmii_latest.tar
- This core implements Physical Coding Sublayer of 1000BaseX transmission (IEEE 802.3 Clause36 and 37). This core can also be used for SGMII interface as this interface leverages 1000BaseX PCS. The differences between the 2 protocols are Link-timer and
3_FirFullSerial
- 基于Quartus II 13.0的FirFullSerial工程设计基本流程，内含详细doc文档-Based on Quartus II 13.0 FirFullSerial basic engineering design process, it contains a detailed doc document
cpu2
- 这是在vivado平台上编写的多功能流水线cpu的实现，是我们课程实验的大作业(This is the implementation of the multi-functional pipelined CPU written on the vivado platform. It's a big job for our course experiment.)
qpskddc
- fpga实现dds和下变频。DDS 技术具有频率切换时间短，频率分辨率高，频率稳定度高，输出信号的频率和相位可以快速切换，输出相位可连续，并且在改变时能够保持相位的连续，很容易实现频率、相位和幅度的数字控制。它在相对带宽、频率转换时间、相位连续性、高分辨率以及集成化等一系列性能指标方面远远超过了传统频率合成技术。因此在现代电子系统及设备的频率源设计中，尤其在通信领域，直接数字频率合成器的应用越来越广泛。-fpga implementation dds and downconversion. DD