资源列表
arb
- verilog round robin arbiter
clk_gen
- 基于vhdl的分频器模块设计，已经经过调试，可直接调用-Divider vhdl module based on the design, debugging has been directly call
less
- Less for VHDL Project
clkdiv
- 初学者一个比较容易入门的FPGA verilog 二分频实验。-Relatively easy for beginners to get into a FPGA verilog two-way experiment.
simple_test
- This a vhdl code for colour converter fpga code for testing shape_gen code-This is a vhdl code for colour converter fpga code for testing shape_gen code
cfq8
- 基于Quartus仿真软件verilog语言的八位二进制乘法器，用于八位二进制乘法运算。-Based on Quartus simulation software of eight binary multiplier, verilog language used in eight binary multiplication.
jkff_behav.v
- This is JK-FF in Behavioural Style.
handshake
- Handshake module detection
CRC32
- 基于FPGA平台的用verilogHDL设计的CRC32模块-a code for CRC32 based on FPGA by verilogHDL
matriled
- led显示器应用相当广泛，数码管的应用也很广泛，本设计就led驱动，数码管驱动进行了设计，设计中采用VHDL语言，在FPGA上实现了功能方真，在开发板上实现功能。-led driver， led scan
vhdl
- 实验内容，为存储器 验证存储器的工作原理，需用实验箱-Experiment content, in order to validate memory memory works, need to use test case
8jiafaqi
- 利用此程序可以实现8位超前进位加法器的功能-This program can be used 8-bit look-ahead adder function