资源列表
fenpin
- 此程序为对外部时钟进行500000分频，采用VHDL语言编写。-This program is on the external clock frequency 500000, using VHDL language.
Mitra_16x16
- 16*16 Withd Mitra font for LCD
shiftreg
- Shift regisiter altera de1 board example
clkdiv
- 一个二分频的verilog代码-A divide-the verilog code
scr
- 60进制计数器同步置位30异步复位 modelsim仿真代码含激励 自己写的 可用 仅供参考入门-60 binary counter 30 the asynchronous reset modelsim simulation code containing motivate yourself to write synchronization set can be used for reference only entry
uart_control
- 用verilog 实现的简易串口驱动模块儿，引脚简单，易用，可自己增减配置-verilog uart
ps2_key
- 使用Verilog完成的电脑键盘PS2协议的驱动。代码中标注了较详细的注释。-Done using the Verilog PS2 keyboard protocol driver. Code marked more detailed comments.
splitscreen
- 分屏算法，将一个屏分为两个屏，两个屏的像素等于一个屏的像素-splitscreen algorithm，used to split one screen into two screen
ADDER
- 超前进位加法器。时序好，功能可靠.工程引用已经验证。-Lookahead adder. Timing is good, functional and reliable
16bitcounter
- it contain source code for 16 bit counter module.
a1
- 1 bit MUX 用ISE写的1bit MUX的verilog code 可以在ISE上模拟1bit MUX的运作-1 bit MUX It is a file of verilog code to design a 1 bit MUX. It is design by ISEbit
mb_rcver
- vhdl，1553b接收模块，为以后的解码和过滤提供稳定的输入。-the 1553b receiver mode, provide a proper input for the 1553b s caodec and fliter