资源列表
crc
- CRC循环冗余检错Cyclic Redundancy Check-Cyclic Redundancy Check
2
- 格雷码转换 计数器的实现 两个程序的实现-Gray code conversion Implementation of counter
mult
- used for multiplexing
dc1
- 40hz sharp with low space and maja -40hz sharp with low space and maja maja
MULTIPLICATER_AND_ADDER
- 本程序描述了实现函数y=ax+b（a和b 都为小于1的8bit小数）的硬件电路描述，最后得到的结果只取了整数部分，为8 bit输出，并且对小数部分四舍五入了。-This procedure describes the implementation function y = ax+b (a and b are less than 1 8bit decimal) descr iption of the hardware circuit, the final result just take the
gen_divd
- FPGA分频器，verilog语言版本，通过实例化参数实现任意整数倍分频-FPGA divider, verilog language version, by instantiating an arbitrary integer multiple parameters Divide
eepromFINALcorto
- Basically it waits for a interrupt (push button) and checks if an eeprom 24c64 has FF in all its address then turns a led if true, this is only if the switch in port D is closed, if not, it writes a byte number "i" in the adress number "i" and then v
SA_VHDL-
- a simple serial adder in vhdl, enjoy it
led
- 51单片机与FPGA led闪烁程序-51 single-chip FPGA led blinking and procedures. . . . . . . . . . . . .
key_scan
- 基于fpga的键盘扫描模块vhdl描述，可以直接调用-Fpga-based keyboard scan module vhdl descr iption, you can directly call
one_clk
- Verilog 中 1:1 分频 电路，实践中可能会用到，这种方法，我也想了很久 -verilog frequency
E_Memory
- memory code with 64 bytes of capacity in vhdl