资源列表
comparator-using-vhdl
- vhdl code for comparator
N-jishu-fenpin
- N倍奇数分频器源码,可根据需要修改N数字即可-N times odd divider source
gdi1
- Viterbi decoder is used for decoding data encoded using Convolution Forward Error Correction codes or data that suffers inter-symbol interference. They occur in a large proportion of digital transmission. Viterbi decoders employed in digital wire
sram_16bit_512k
- FPGA 的sram controller -it is a certifed sram controller
edge_check2
- 一种实用的上升沿检测程序，可用于上升沿检测，或根据上升沿生成高低电平等-Rising edge of a practical testing procedure can be used for rising edge detection, or generated in accordance with the high-low, such as rising edge
ModifyInstruction
- 数字环路滤波器是由变模可逆计数器构成的。 该计数器设计为一个17 位可编程(可变模数) 可逆 计数器,计数范围是,由外部置数DCBA 控制-Digital loop filter is composed of variable-mode reversible counter. The counter is designed to a 17-bit programmable (variable modulus) reversible counter, counting range is s
fpga-4
- VGA controller and display wit h eight coloreight coloreight coloreight color s displayedisplaye displayedisplayedisplayed in a fixed ordea fixed orde a fixed orde a fixed ordea fixed orde a fixed order.
uart_tx
- uart transmitter module in verilog hdl
encrypt_8
- This vhdl source is top level entity. TEA algorithm to encrypt 8-bit data.
dac8552
- FPGA中利用状态机实现串并转换，读取dac8552数据-FPGA utilizing state machine string and conversion, data read dac8552
SEG7_LUT_8_0
- DE2开发平台7段显示VHDL代码，自己针对vilorg翻译成VHDL代码-DE2 Development Platform 7 show the VHDL code for vilorg translated into their own VHDL code
div_2m_to_2
- 将2MHz信号分频成2Hz信号的分频器，多用于指示灯的显示，实际使用过。-2MHz to 2Hz divider