资源列表
gen_clk
- 占空比可变的信号发生器 解释的好麻烦那 不知道怎么解释-A variable duty cycle signal generator
MediaMobile
- moving average vhdl source code
asyncwrite
- FPGA异步时序转同步时序模块 位宽（bit） -FPGA asynchronous transfer timing synchronization timing module Width (bit)
conv
- conv clock code for any thing
NO2_SWITCH_IF
- swiych_if by vhdl using xlinx
8-bitinput-output-shift
- 8位串行输入，串行输出移位寄存器 VHDL-8-bit serial input, serial output shift register VHDL
max5822
- Arduino Program for pulsing the brightness of an LED connected to a MAX5822 DAC chip to Arduino Duemilanove Microcontroller. 88 is the I2C address of the DAC chip, Please refer to MAXIM s official datasheet for better understanding of the DAC
main
- 实现两个8°的音阶，储存有一首音乐，用lcd显示-Two 8 ° scale, stored in a music, with lcd display
basketball24
- 基于FPGA的篮球24秒计时器，开发环境为MAXPLUS-24 second timer in the FPGA-based basketball,Development environment for MAXPLUS
plx_r
- vhdl中的频率锁相环部分，完成时钟配置-part of the frequency locked loop vhdl complete clock configuration
ls_led
- 实现流水灯的程序，适合初学者参考和学习。-Achieve light water program, suitable for beginners reference and learning.
zuoye60
- 基于VHDL的60S倒计时设计，附带数码管显示，倒计时完成后蜂鸣器报警-60S countdown VHDL-based design, with a digital display, the countdown is completed after the buzzer alarm