资源列表
fifo
- 用VHDL语言写的FIFO代码，可设FIFO的深度-VHDL language with code written in FIFO, FIFO depth can be set up
mux41we
- 4:1 multiplexer using with select.. Test Bench included-4:1 multiplexer using with select.. Test Bench included..
duble-process-lock
- 编写由两个主控进程构成的与上述功能相同的符号化Moore型有限状态机-The process of writing composed by two main control functions with the same symbol of Moore-type finite state machine
lcd1602
- verilog写的v5板子1602测试程序 可以直接使用 已测试-this is a code applied for lcd1602 in v5
read_file_test
- VHDL读写文件范例，仿真专用，验证通过-Examples of VHDL to read and write files, simulation-specific, verified by
count
- 自己编制的计数器的verilog代码 希望能对大家有所帮助
sseg
- vhdl codefor 7 segment display
24add
- 24进制it describe how to design a add24-it describe how to design a add24
USB
- 这个是Verilog的USB控制程序，用于USB与FPGA之间的通信-This is the USB Verilog control procedures for the communication between USB and FPGA
jiaotongdeng
- 显示模块包括数码管动态扫描电路和译码显示电路，动态扫描电路用于选择需要显示的数码管，译码显示电路用于将输入的二进制信息转换为数码管显示编码。显示模块中使用四个数码管显示倒计数值，两个用于显示东西方向倒计时值，两个用于显示南北方向倒计时值，使用四组红、黄、绿发光二极管显示通行、进行和转弯。由于没有转弯控制信号灯，所以使用红灯、绿灯亮黄灯闪烁作为转弯的指示信号。-The display module includes a dynamic scanning circuit and decoding o
zhuangtaiji
- vhdl状态机程序，经实验验证，没有错误！完美运行，可以用以了解状态机的初步应用！-vhdl state machine program, proved by experiments that there are no errors! Perfect run, can be used to understand the initial application of the state machine!
ClockGen
- ClockGen code in VHDL for Xilinx Spartan 3E board