资源列表
jianfaqi
- 8位减法器，我在quartus 9.0版本上运行正常，大家放心下载-8-bit subtractor, I run the normal version of quartus 9.0, we rest assured Download
www_onlylz_com@b-do84mw
- nois2 开发实例。应用平台是DE2开发板。实现一个简单的电子时钟的显示万年历。设计简单，便捷-nois2 development instance. The application platform is DE2 development board. Implement a simple electronic clock display calendar. The design is simple, convenient
VGA_VHDL
- VGA 视频 VHDL 原代码, 当然你需要FPGA板去调试改变. 仅仅看作好的原始参考-VGA video VHDL source code, of course, you need to FPGA board to debug changed. Merely as good the original reference
rim_top
- this is source usinf fifo source xilinx thank you.........................
b2d
- 使用Verilog语言编写的2进制转10进制程序-Using Verilog language binary program turns 10 decimal
CPLD任意分频输出 VHDL
- CPLD任意分频输出 VHDL,调试通过
4to2
- 4對2解碼器 利用CASE方式來做選擇 較類似C語言-4 2 decoder to use to make a choice of more CASE manner similar to C language
Gray-Counter
- 格雷码，用于理解格雷码的的功能，减少出错。同样对于卡诺图很用吧。-Gray code, Gray code, the function used to understand and reduce errors. The same for the Karnaugh map.
shft_reg_8_vhdl
- this a shift register vhdl code-this is a shift register vhdl code
keeloq encoder
- this code is a keeloq encryption verilog code-keeloq encryption verilog code
sort
- 這個是排序,它可以幫妳把妳像要的數值進行排序-This is the sort that can help you turn on your values to be sorted as
fenpinqi
- 分频器部分 参考这个是对的 但是请与自己的程序相匹配-Part reference divider, but this is the right procedure for you and your match