资源列表
eda2
- 一个带记数使能，同步复位，带进位输出的增一 六位二进制记数器，记数结果由共阴极七段数码管显示-One with a count enable, synchronous reset, into digital output by 16 binary counter, counting the results from the common cathode seven-segment LED display
spi_dac
- driver for spi DAC in VHDL
New-folder
- Vhdl codes for D flip flop and so
VGA_Controller
- vga的行场信号驱动，由verilog编写，需提供25M的时钟驱动，为640*480的大小。-vga signal field lines driven by the verilog writing, must provide the 25M clock drive, the size of 640* 480.
shijinzhishumaguangundongxianshi
- 数电实验作业：十进制计数的数码管滚动显示(VHDL源程序)-Decimal count digital tube scroll (VHDL source)
pso-vhdl
- i have verilog and VHDL coding. please help me.
divider
- VERILOG编写的24位除法器代码核，是FPGA或者ASIC设计中的一核心计算模块。-VERILOG written 24 divider code nuclear FPGA or ASIC design in a core module.
biaojueqi
- 七段显示译码器，在学习中是一个经典案例，值得认真学习-Seven segment display decoder, in a classic case study worthy of serious study
clock
- 大学生篮球比赛30S计时器-30S college basketball game timer
sqrt
- VERILOG描述的开平方模块核，开方运算是FPGA或ASIC设计中所需要的核心运算模块。-VERILOG descr iption of open square modules nuclear root operation is the core computing module FPGA or ASIC design.
demodulation
- QPSK解调程序，verilog语言，基于FPGA的硬件描述语言-QPSK demodulation
code
- 动态扫描键盘，然后把按键结果显示在LCD上，相关使用去抖功能-Dynamic scan keyboard, and then the key results are displayed on the LCD, the use of the shake function