资源列表
bram_block_0_wrapper
- 赛灵思FPGA开发板上BRAM模块VHDL源代码，可作为硬件设计参考资料！-Xilinx FPGA development board BRAM module VHDL source code, hardware design can be used as reference!
5t
- sram design is it,u can see its easy ,so i upload it here my frnds it is useful code see this it is in vhdl language
24
- 基于6M晶振FPGA的篮球24秒计时器verilog HDL代码，附testbench-Verilog HDL code for FPGA-based 6M crystal basketball 24 seconds timer, with testbench
control
- 微程序控制器的VerilogHDL代码，24位微指令，一般用于CISC控制器的设计-Micro-program controller designed VerilogHDL code, 24 microinstruction, generally used for CISC controllers
code
- clk_sys为输入时钟，rst为复位信号，clk_out为输出分频时钟，div_num为分频数目。多少分频就把div_num赋多少值。-awet.etr.ert.ewtewjtr eqtr ert ert ewr erwrt ewrt ret5 asd er.
AT24c512_Test
- A simple program to read AT24C512 (512KBit, I2C, EEPROM) memory in Arduino environment.. This program usefull to test connectivity and development.
8.6-DAC0832
- DAC0806的程序代码，本人已通过验证-DAC0806 program code, I have verified
shenfaqi
- 設計一個除法器電路，輸入 8 -位元的被除數 A 與除數 B ，輸出為商 Q=A/B及餘數R。-Design a divider circuit, type 8- bit of the dividend A and divisor B, output of business Q = A/B and the remainder R.
1
- 128X64的点阵的显示 在8051的环境下实现 使用keil C的编译环境-the dot display for 128X64
RT-DATA
- 61580 1553b rt 芯片驱动程序 地址-61580 1553b rt address
manchester-encoding-VHDL
- 曼彻斯特编码解码的代码，在网上找到的。因为毕设需要找到的，特此分享。-Manchester encoding and decoding the code found on the Internet. Need to find the complete set, is hereby share.
booths
- booths multiplier vhdl program