资源列表
VHDL_reg
- 用vhdl写的有关寄存器的源代码，适合于硬件开发入门。
ddsm
- 用vhdl实现dds功能的程序试一试看看是不适合你！-Dds feature using vhdl program to try to achieve a look is not for you!
multiply
- 简单的乘法器，用Verilog实现 multiply-multiply
booth
- modified booth recoding in vhdl
lcd1602
- lcd1602的vhdl程序，改程序只能显示字符和数字，不能显示汉字-lcd1602 the vhdl program, change the program can only display characters and numbers, can not display Chinese characters
Diminishing-points-frequency
- 外接50M晶振，可分频为20、10、5、1KHz的占空比为50 的递减分频-External 50 M crystals, can divide frequency for 20, 10, 5, 1 KHz accounted for more than 50 of the empty diminishing points frequency
VHDL
- 组合逻辑电路设计：基本逻辑门、三态门、译码器。-Combination logic circuit design: basic logic gates, tri-state gate decoder.
driver
- 基于FPGA的脉冲发生，使用的是Quartus仿真环境以及VHDL语言编译-FPGA-based pulse generation, using Quartus simulation environment and VHDL language compiler
bram_block_0_wrapper
- 赛灵思FPGA开发板上BRAM模块VHDL源代码，可作为硬件设计参考资料！-Xilinx FPGA development board BRAM module VHDL source code, hardware design can be used as reference!
5t
- sram design is it,u can see its easy ,so i upload it here my frnds it is useful code see this it is in vhdl language
24
- 基于6M晶振FPGA的篮球24秒计时器verilog HDL代码，附testbench-Verilog HDL code for FPGA-based 6M crystal basketball 24 seconds timer, with testbench
control
- 微程序控制器的VerilogHDL代码，24位微指令，一般用于CISC控制器的设计-Micro-program controller designed VerilogHDL code, 24 microinstruction, generally used for CISC controllers