资源列表
divNfreq
- 参数化分频器，以5为例，能很方便的扩展到参数N-osedge and negedge using common counter "cnt" parameter N is the double number of frequence division
uvo_role
- 用户角色模型的函数，模仿window，版本为PB-A function of user role model, imitation window, version PB
ssram-and-tesebench
- 实现一个256x8的同步静态存储器SSRAM，用硬件描述语言Verilog写的，同时谢了测试程序-it realized a 256x8 SSRAM,writen by Hardware descr iption language Verilog ,and include the testbench.
IQDemod
- the I_Q Demoder is usefull for communication process in FPGA
pwm_generate_module
- verilog编写的，用按键控制PWM波占空比。可以定义死区，用来控制舵机或者led灯的亮暗。-Verilog prepared, with the button to control the PWM wave duty cycle. You can define the dead zone, used to control the steering gear or led lights bright and dark.
sram_test
- SRAM模块功能描述，扩展运用外部存储器实现其他功能时可选用-SRAM module functional descr iption, extended the use of external memory for other functions, i.e.
mod_m_counter
- Frequence Divisor for the Universal Received Transmitter
juanji
- FPGA的卷积编码小程序，VHDL描述，参数为2，1，7.-2,1,7 cov with VHDL.
WBUart
- Verilog实现的Uart模块，在quartus9.1环境下已综合、运行成功。-Verilog implementation Uart module has been integrated in the quartus9.1 environment, run successfully.
verify_crc
- Verifcation module for CRC with polyn = "10010111" -Verifcation module for CRC with polyn = "10010111"
RC17871ASW
- 用于控制RC7871芯片工作程序，可控制IC工作状态切换及其他-for RC7871 Contorl
jpsm
- 基于VHDL语言的4*4矩阵键盘扫描代码-Matrix keyboard scan