资源列表
rs_enc
- 这是一个用VHDL编写的RS信道编码程序-This is a VHDL prepared with RS channel coding procedures
movedata
- 按照一定格式把一段数据放在内存上，然后输出在屏幕上-my asm
clk_gen
- 基于fpga的分频器的vhdl描述，可以直接调用，只需修改一些参数-Fpga based on the divider vhdl descr iption, can be directly called, simply changing some parameters
SPI_Port
- VHDL 实现SPI接口、并行数据输入，SPI接口数据输出。-VHDL to implement the SPI interface, the parallel data input, SPI interface data output.
Hex_decoder_7seg
- 十六进制显示译码器，VHDL语言的设计，根据高低电平的变化进行数码管的数字显示-Hexadecimal display decoder VHDL language design, high and low changes in the number of digital tube display
sine
- 简易的正弦信号发生器，用verilog代码写成-A simple sinusoidal signal generator, written with verilog code
8-Bit-Simple-Up-Counter
- 简单的，计数器，上升沿有效。经过ise13.1测试，完全符合逻辑-Simple, counters, and the positive edge. Tested
ade
- Verilog code for modified serial multiplier
counter
- A 4 bit counter. In the testbench I combine three counters into one. Verilog codes with testbench.
mux-top-module
- Vhdl implementation of Mux module using and gate or gate and with testbench
paral_to_serial
- 用verilog HDL编写的并行接口转串行接口的程序。-The programming of parallel interface to serial interface with HDL verilog.
Filtro
- Digital filter in VHDL