资源列表
fir16_12_2m_hamming
- VHDL语言fir16_12_2m_hamming的描述 里面有详细的程序代码-fir16_12_2m_hamming
decrypt_controll
- controller for fast_aes128. Sends start and load pulses at a lower clock than main_clk.
SMG_DISPLAY
- 4位一体共阴极数码管显示模块，调用模块，直接显示-SEG display module
Program3
- Simple VHDL program using counters
baseband_modulation_coef_gain
- CPM调制定点增益模块，完成CPM的调制指数确定-Phase locked loop demodulation module, for CPM modulation demodulation front end
cnv_encode
- （2,1,7）卷积编码器,用于产生卷积编码 G1(X) = 1 + x + x^2 + x^3 + x^6 G2(X) = 1 + x^2 + x^3 + x^5 + x^6 -（2,1,7）cnvcode G1(X) = 1+ x+ x^2+ x^3+ x^6 G2(X) = 1+ x^2+ x^3+ x^5+ x^6
Adder12_3-4
- This is an 12 bits adder in Verilog. it adds three 4 bit nibbles in parallel.
weiji
- 基于FPGA的UART设计，fpga简单的波特率发生器设计-FPGA-based UART design, fpga design simple baud rate generator
black_jack
- verilog编写的21点游戏，用状态机写的，A可以表示1也可以表示11.-verilog 21-point game, written by a state machine
adder
- This code implement add between 2 number
fulladd4bit
- 這是全加器,名字為fulladd4bit.rar,功能為四位元的加法。-This is the full adder, the name of fulladd4bit.rar function is the addition of four bits.
ram
- 基于VHDL的教学实验机ram芯片连续读写-RAM chip based on VHDL continuous read and write