资源列表
Example-3-1
- 经过验证的经典实例，完全正确的。适合于入门新手的实例，仅供交流使用。-fpga exampe
SMG_DISPLAY
- 4位一体共阴极数码管显示模块，调用模块，直接显示-SEG display module
Program3
- Simple VHDL program using counters
baseband_modulation_coef_gain
- CPM调制定点增益模块，完成CPM的调制指数确定-Phase locked loop demodulation module, for CPM modulation demodulation front end
cnv_encode
- （2,1,7）卷积编码器,用于产生卷积编码 G1(X) = 1 + x + x^2 + x^3 + x^6 G2(X) = 1 + x^2 + x^3 + x^5 + x^6 -（2,1,7）cnvcode G1(X) = 1+ x+ x^2+ x^3+ x^6 G2(X) = 1+ x^2+ x^3+ x^5+ x^6
Adder12_3-4
- This is an 12 bits adder in Verilog. it adds three 4 bit nibbles in parallel.
weiji
- 基于FPGA的UART设计，fpga简单的波特率发生器设计-FPGA-based UART design, fpga design simple baud rate generator
black_jack
- verilog编写的21点游戏，用状态机写的，A可以表示1也可以表示11.-verilog 21-point game, written by a state machine
adder
- This code implement add between 2 number
grantyz
- 4倍频鉴相功能模块，利用Verilog hdl语言编写的-4x phase function module using Verilog hdl language
clock_retrive_lsy
- 用于E1接口数据时钟恢复，可提取相应的频率-Using for E1 interface, support 2M frequency recovery and retime
IQ_sin_cos
- Cordic根据输入的IQ正交两路信号求取对应的正余弦值-Cordic according to input the IQ of orthogonal cosine signal to calculate the corresponding two road is