资源列表
adder44
- adder 4 + 4 bits, for use with a Altera, and 2 displays 7 segments-adder 4+ 4 bits, for use with a Altera, and 2 displays 7 segments
Example-3-1
- 经过验证的经典实例，完全正确的。适合于入门新手的实例，仅供交流使用。-fpga exampe
reg2
- Register2 Project VHDL
clkdiv
- 占空比可调 分频系数 都可随意设定的分频器，语言为Verilog HDL-Duty cycle factor can be freely adjustable frequency divider set the language for the Verilog HDL
aahr
- vhdl下编写的rom,vhdl专用这个编程能帮你学习到老-it s very good!when you download this one ,it s good for your study
di3
- IP核和乘法运算模块分别有两个输入端口a、b和clk时钟脉冲信号及一个输出端口p，用例化语句将这两个模块合成一个乘法器后就生成了由两个输入端口a、b和clk时钟脉冲信号及两个输出端口p1、p2组成。-IP cores and multiplication module respectively, the two input ports of a, b, and clk clock signal and an output port p, these two modules with the in
matlabtomodelsim
- matlab to model sim converter coding of vhdl code ypu want to convert that matlab into the xilinx platform model sim simulator
laser_timer
- laser timer source and test bench code 4
Stepper-motor
- 步进电机驱动模块设计，使用硬件描述语言设计。-Stepper motor driver module design, using a hardware descr iption language design.
grantyz
- 4倍频鉴相功能模块，利用Verilog hdl语言编写的-4x phase function module using Verilog hdl language
clock_retrive_lsy
- 用于E1接口数据时钟恢复，可提取相应的频率-Using for E1 interface, support 2M frequency recovery and retime
IQ_sin_cos
- Cordic根据输入的IQ正交两路信号求取对应的正余弦值-Cordic according to input the IQ of orthogonal cosine signal to calculate the corresponding two road is