资源列表
Clock_Edge
- The Audio Core interacts with the Audio CODEC (enCOder/DECoder) on the Altera DE2/DE1 Boards and provides an interface for audio input and outpu
fir
- vhdl code for fir filter
adder_32
- 32bits 加法器-32bits adder
UART
- pic16f4011 实现异步通讯，可以直接用-pic16f4011 UART
clkdiv
- vhdl实现任意分频，在fpga上测试成功，只需修改一个变量即可实现任意分频-Arbitrary frequency
light
- 用vhdl语言实现交通灯控制，可以用quartus2软件打开并仿真，经本人仿真无误。-Vhdl language used to control traffic lights can be turned on and quartus2 software simulation, simulation accuracy, as I am.
5
- 4*4矩阵状态机键盘 是数字电路设计中常用的信号输入法-4* 4 matrix keyboard state machine is commonly used in digital circuit design, signal input method
Tristate_driver
- it contain source code for tristate driver module.
thermometer-control
- this a digital thermometer control program using 8051 micro controller and LM35 temperature sensor-this is a digital thermometer control program using 8051 micro controller and LM35 temperature sensor
Uart_2
- ＳＴＣ单片机的串口模块可以采用Ｔ１定时器作为它的波特率发生器，同时其内部也集成了一个独立波特率发生器作为串口的波特率发生器，本例子采用的是常用的独立波特率发生器ＢＲＴ作为它的波特率发生器-STC microcontroller serial port T1 timer module can be used as its baud rate generator, while its interior also incorporates an independent Baud Rate Genera
clk_div3.5
- 用VHDL实现的带清零的3.5分频的代码。调试通过。-Implemented in VHDL with a clear frequency of 3.5 code. Debugging through.
two_fsk1
- 基于verilog的2fsk调制的程序，调试通过，有需要可以下载来参考 -Based verilog of 2fsk modulation process, debugging through, there is a need to download reference