资源列表
div_1p5
- 时钟1.5分频的Verilog代码，简明扼要！-Clock frequency of 1.5 Verilog code, clear and concise!
4
- Verilog写的 8 位超前进位加法器-Verilog write 8-bit CLA
verilog
- 经典verilog实例，将近130多个。包含大部分设计基础实例，有益于初学者学习。-Classic example of verilog, nearly more than 130. Contains examples of most of the design basis, the benefit of beginners learning.
counter
- This a simple Counter -This is a simple Counter
tcounter
- tcounter vhdl descr iption
interleaver
- vhdl code for interleaver
DIVIDA
- 20位除法器，vhdl语言所写的，不错的代码，仅供参考-20 divider, vhdl language written
cs
- 计数器设计结果用七段数码显示译码器设计,-Counter with seven segment digital display design results decoder design,
dff1
- --学习D触发器的原理 --按下学习板的KEY1键，LED灯会显示状态 --按下按键，对应的I/O是低电平。所以LED灯会亮?-- Learn the principles of the D flip-flop- Press the learning board of KEY1 key to display the status LED Lantern- press the button, the corresponding I/O is low. So LED lights?
verilog_pwm_led
- 基于fpga的pwm灰度控制led代码，简洁易懂-FPGA-based control led pwm gray code, simple and easy to understand
Reg_4bit
- Uploaded code to design 4 bit register.
gen_div
- 通用偶数分频器，通过输入频率较高的时钟信号，在设置分频参数后，得到较低频率的时钟信号。-gen div