资源列表
4
- Verilog写的 8 位超前进位加法器-Verilog write 8-bit CLA
verilog
- 经典verilog实例，将近130多个。包含大部分设计基础实例，有益于初学者学习。-Classic example of verilog, nearly more than 130. Contains examples of most of the design basis, the benefit of beginners learning.
counter
- This a simple Counter -This is a simple Counter
tcounter
- tcounter vhdl descr iption
interleaver
- vhdl code for interleaver
sw_led
- _sw_led 拨动开关控制LED-_sw_led toggle switch controls the LED
VENDTEST
- 此为实现第14.7.9章所需的激励文件 该代码为门级RTL描述。-Stimulus file to verify Section 14.7.9 the functionality of gate vs. RTL descr iption.
unsig_altmult_accum
- 无符号型的基于累加器的乘法器，代码比较简单-unsigned altmultiplex accumultor
UniformRNG
- A Uniform Random Number Generator in VHDL
verilog_pwm_led
- 基于fpga的pwm灰度控制led代码，简洁易懂-FPGA-based control led pwm gray code, simple and easy to understand
Reg_4bit
- Uploaded code to design 4 bit register.
gen_div
- 通用偶数分频器，通过输入频率较高的时钟信号，在设置分频参数后，得到较低频率的时钟信号。-gen div