资源列表
contador_n_bits
- n-bits counter vhdl with testbench. contador de nbits en vhdl con simulacion.
vhdl_fir
- 1、输入输出数据宽度为12位， 2、阶数为4阶段线性相位FIR滤波器， 3、类型为：低通。 -1, input and output data width is 12, 2, 4 stages of the order of linear phase FIR filter, 3, type: low pass.
Buffer8x32
- Para controlar el flujo del algoritmo SHA
decoder_using_with
- decoder_using_with verilog code
Karasimsek
- A VHDL implementation of Karasimsek
Adder4bit
- VHDL full adder 4 bit
waterline_adder.rar
- 这是一个用Verilog编写的四级流水线加法器,This is a Verilog prepared with four pipeline adder
sqrt
- 实现任意位数的开方算法，但是不是浮点的算法，-Square root algorithm for arbitrary digit, but not floating-point algorithm, thanks
HDB3-Decoding
- hdb3解码程序，输入时01代表+1,10代表-1,程序经仿真通过。-hdb3 decoder, input 01 representative of the representative+1,10-1, the program adopted by the simulation.
AND_gate
- VHDL AND gate source code
sine.txt
- THIS IS CODE FOR VHDL
Input_filter
- Module for filtering input digital signal