资源列表
tcounter
- a counter t in vhdl with flip-flop tipe t
tb_tx_modem
- test bench for tx modem to make simulation for ofdm based system
seg7led
- quartus 2七段管的html语言实现-quartus 2 html language seven sections of pipe
NAND_gate
- VHDL NAND gate source code
cnt10
- 超好用的十进制计数器，万能型，随时可用，好用好用好用，VHDL经典例子-perfect counter10，very very good，can be used everyehere，classical example
FFT
- FFT在NIOS2上的的实现。通过AD给的值。-In the NIOS2 FFT realization.Through the AD to value.
dp
- datapath code in verilog for pipeline processor
generator
- generator of functions for vhdl
booth_mul
- 乘法器 基于改进booth编码 已验证 clk-multiplier modified booth
mc
- 可控脉冲发生器:采用1KHz的工作时钟，初始化周期为2.5s，占空比为50 ，所以周期（T）初始化为2500，占空比（Result）初始化为1250；用按键S1、S2、S3、S4分别实现周期增大、周期减小、占空比增大、占空比减小。-Controllable pulse generator
simple_ram
- the file about simple ram by VHDL code
fulladdr
- full adder source and test bench 5