资源列表
fifo
- A First in first out buffer in Verilog
dds
- da的代码,在VHDL的编译环境下的开发。是一种集约的形式。-DA convert
pwm
- VHDL编写的PWM波控制LED亮度的程序。-Written in VHDL wave PWM LED brightness control procedures.
OR_gate
- VHDL OR gate source code
ram
- 一个简单的ram,自己写的。希望对大家有用-A simple ram, write your own. Hope to useful
counter
- module counter for VHDL on FPGA Kit
4位乘法累加器
- 4位乘法累加器,有需要的下吧,其他位的可以自行修改~-Multiplication accumulator 4
eightbitLatch
- 一种8位锁存器,程序简单,为初学者提供,一种简单的数据锁存方式。-a kind of eight bits latch。
Encoder8_3
- this is a source code for 3 is to 8 decoder
binary_adder_subtractor
- binary adder / subtracter in vhdl
4bitmultiplier
- its a verilog coding of a multiplier. it multiply 2 values each of width having 4bit
ls74160
- VHDL设计的160集成电路,仿真测试正确,可以使用。-160 IC VHDL design, simulation tests correctly, can be used.