资源列表
cnt8updown
- 8位上下同步计数器 适宜小型练手操作 易于理解(an 8-bit up and down synchronous counter in VHDL with the following features: (1) The same ports are used for signals to be inputted and outputted. The ports are bi-directionally buffered (three-state). (2) The counter is
2_4decoder
- 三种描述风格的VHDL代码，快速建立不同风格描述语言的概念及结构(Three styles of VHDL code to quickly establish the concept and structure of different style descr iption languages)
tt
- VHDL Implementation of decade counter
State_machine_1
- VHdL code to implement simple state machine
bcd_to_dec
- VHDL code for converting BCD to Decimal
disp1
- VHDL code for 7 segment display nexys 3
uart_receiver
- Uart receiver VHDL code
uart_working_transmit
- UART transmission vhdl code, for nexys 3 fpga board
uart_rx
- UART FPGA串口发送程序，已经调试通过，可以放心使用，谢谢，(Serial transmission program, has been debugged, can be assured to use, thank you)
verilog_vga_code
- 基于VERILOG语言的VGA显示程序，自己编写，亲自测试(VGA display program based on VERILOG language)
FPGA_SDRAM
- 基于Verilog语言的SDARAM代码(SDARAM code based on Verilog language)
VERILOG_USB2.0源代码
- 基于verilog针对CY68013开发的USB通信程序(USB communication program based on Verilog for CY68013 development)