资源列表
binary-and-gray
- 二进制码和格雷码互相转换verilog源码-Binary code and Gray code conversion verilog source
xds100v2-CPLD
- xds100v2 CPLD 源码 配置 xds100v2 CPLD 源码 配置-xds100v2 CPLD SOURCE xds100v2 CPLD SOURCE
ledscreen
- FPGA上lcd屏幕显示控制程序，verilog代码-Lcd screen display program . Codeing in Verilog HDL .
IFFT
- 使用ISE开发环境实现802.11a物理层OFDM系统中逆fft模块-ISE development environment inverse fft module 802.11a physical layer OFDM system
good
- FPGA电机电流矢量控制程序,用vhdl语言编写-vector control IP in vhdl for fpga
QDEC
- 旋转编码器的正交解码程序，使用VHDL语言--- This decoder in VHDL samples the signals using all four available edges of -- A and B. E.g. sample(B) on rising(A), sample(A) on falling(B), sample(B) on -- falling(A), and sample(A) on rising(B).
Taxi-Charging-VHDL
- 一个用VHDL写的出租车计价器例子，采用数码管显示，对里程和费用的显示计算。-Taximeter example, to write a VHDL digital display that displays the calculated mileage and expenses.
sdramtest
- vhdl语言编写读写三星SDRAM程序，包含读写控制程序，地址转化程序，测试模块程序-vhdl language, reading and writing the Samsung SDRAM program, contains the read and write control procedures address conversion program, the test module program
dpsk_3rd
- 2DPSK调制与解调。学生实验使用，包括信号源模块、时钟源生成模块、信号调制模块，信号解调模块。 其中包含了边沿触发下的阻塞语句。 编译环境：Q2 11.0，编译语言：verilog，仿真软件：moelsim altera -2DPSK modulation and demodulation. The student experiments, including the source module clock source generation module, signal modu
bianma
- 用verilog编写的实现相位选择的DQPSK调制-Written in verilog DQPSK modulation phase selection
inout-vhdl
- c p u 读inout 端口的vhdl 程序-Read inout port vhdl program
jiaotongdeng
- 简易的交通灯程序，适用于刚接触VHDL的人学习，易懂好学。-Simple traffic light program, for people new to VHDL to learn, easy to understand studious.