资源列表
adder_sub_TB
- adder/subtractor testbench
ad7606
- AD7606采集代码，用于verilog 驱动 AD7606 adc SPI 串口方式(AD7606 acquisition code, used for Verilog drive AD7606 ADC SPI serial mode)
emif
- fpga emif 通信接口软件设计基于fpga(FPGA EMIF communication interface software design based on FPGA)
SPI_Master
- spi 主发送模块，功能已测试没有问题，各个信号已标注(SPI main send module, the function has been tested, no problem, each signal has been marked)
make_pwm_block
- 内置宽度和频率寄存器，可调制宽度和频率得PWM(Built-in registers, width and frequency PWM modulation width and frequency)
syn6288
- 北京一家 语音芯的应用，例子，可以广泛用银行排队机，手持机的播报语音，交互仪器上语单播报等设备上(The application of a voice core in Beijing, for example, can be widely used in Bank Queuing machines, handheld broadcast voice, interactive instruments, unicast devices and other equipment)
adc
- VHDL code of adc and interfacing with Spartan 3E FPGA Board
AD_TO_FIFO
- A/D采集的数据缓存进入fifo，并通过读信号将FIFO中的数据送入网口(A/D sample data buffer to fifo,and then read enable to ethernet.)
hmc960
- hmc960芯片的初始化程序，可以实现verilog程序，微波信号的放大(hmc960 initial code,spi ,verilog,amplify)
slave
- xilinx Zynq 中的AXI总线 axi slaver模块(AXI bus Axi slaver module in Xilinx Zynq)
Carry-Skip Adder
- 经典的进位跳跃、进位选择、并行前缀加法器，16位，基于verilog HDL语言(16-bit carry-skip adder)
y210
- 三八译码器，四位加法器，EDA实验，用verilog编写(EDA experiment with verilog language)