资源列表
CMA
- 用Verilog实现FSE-CMA算法，分为四个模块，一共迭代8次(Implementation of FSE-CMA algorithm with Verilog)
ADM_code
- AD采样转换,采用verilog完成，可直接使用。(AD TRANSMIT using verilog complete, can be used directly.)
f8730f202fe8
- 基于vhdl的pi算法，程序写的很详细，利用整数运算避免使用浮点数(PI algorithm based on VHDL)
pulse_exp
- 可配占空比、脉冲个数，受输入trigger的脉冲产生器(The pulse generator with input trigger can be matched with the null ratio and the number of pulses)
VGA显示汉字VHDL程序
- 使用vhdl语言编写的，通过vga在屏幕上显示汉字(Using VHDL language, through the VGA display Chinese characters on the screen)
color_bar
- 使用verilog编写的模块，输出1080p彩条测试视频，输入时钟频率可以为74.25M或者148.5M(The use of Verilog module, 1080p color video output test, input clock frequency is 74.25M or 148.5M)
odd_even_check
- 用于检查数据的正确性。具体而言，在发送端，通过增加校验位，使有效数据位和校验位组成数据校验码；在接收端，根据接收的数据校验码判断数据的正确性。(For correcting the correctness of the data. Specifically, at the transmitting end, the valid data bits and the parity bits are added to the data check code by adding the parity b
original_code_multiplier
- 16位原码乘法器，附带测试程序，实现两个16位的乘数相乘。(16-bit original code multiplier with test program)
unsigned_array_multiplier
- 4X4位的无符号型阵列乘法器，可以提高乘法的运算速度(4X4 bit unsigned array multiplier, can increase the multiplication of the operation speed)
sequence_detector(6-state)
- 将《Verilog数字系统设计教程》(夏宇闻)一书中第15章的源代码进行了改进，由原来的8状态精简到6状态，同样可以实现要求的功能，对于重叠出现的特定序列也可以检测到。(The source code of Chapter 15 of the Verilog Digital System Design Tutorial (Xia Yuwen) has been improved from the original 8 state to the 6 state, and the required
Desktop
- I2C,测试代码，经过验证调试与，这个测试代码发现是可用的(I2C, test code, verified debugging and, this test code discovery is available)
prj_ex_1
- 基本工程写法仿真和方法，经过具体的仿真和优化，发现代码完全可用(The method and simulation of the locking device are simulated and optimized, and the code is found to be fully available)