资源列表
flash_test
- 使用Verilog HDL语言驱动FPGA读写flash(FPGA read and write flash)
KEYPD
- Keypad sample. Vhdl language
UART
- UART串口通信模块：包括接收模块RXD、发送模块TXD、分频模块FREDIV(UART serial communication module: including receiving module RXD, sending module TXD, frequency division module FREDIV)
ADC
- vhdl analog digital converter
ac_acquire
- ads127l01串联模式，串联了两个芯片，此时最大采样率不能用。osr的值为 01，10，11.(Ads127l01 series mode, in series with two chips, at this time the maximum sampling rate can not be used. The value of OSR is 01, 10, 11.)
OTU_RXBLK
- cctv otu rx block source
kdw_tsohcnt
- cctv otu top source source block
uart
- FPGA的串口通信 v 文件，直接编译就可以串口通信了，波特率9600(FPGA serial communication, V file)
AnalyzePESig
- Project template for cloud computing
Qencoder
- 编码器计数，根据状态机原理，判断编码器所属状态。(Encoder count, according to the principle of the state machine, to determine the state of the encoder)
Cyberoam_SSL_CA
- bandwidth and particularly well suited to high performance PC applications.
apb
- APB 总线。可以实现单个数据在总机与从机之间的读写功能(This can achieve the read and write functions of a single data between the master and the slave .)