资源列表
sccb_Protocol
- 该模块实现了SCCB通信协议的基本时序，经板级调试可用(Implement SCCB communication protocol)
bayer_to_vga
- Bayer 视频流转VGA的Verilog实现，经开发板测试可用(Bayer video streaming VGA Verilog implementation, the development board test available)
comparator
- COMPERATOR 2位比较器，含测试(COMPERATOR 2 bit comparator, including testbanch)
测pwm波占空比
- 基于Verilog的接受pwm波并且测量pwm波占空比(Measuring the duty cycle of PWM wave)
mian
- 系统上电后，数码管低五位显示00000，按下PLUSE按键，显示数值加1(After power on, the digital tube is low, five shows 00000, press the PLUSE button, display the value plus 1)
sine
- 基于FPGA产生正弦波信号，频率可控，很有用(FPGA based sine wave signal generation, frequency control, very useful)
RegCPUData
- 虽然FPGA实现并口输出是一个最简单的，但还是考虑用parameter的参数化方法来配置，这样在使用多个并口时，可以配置并口的宽度和并口的地址，应该更加方便。(Although FPGA parallel output is one of the most simple thing, but still consider using the parametric method to configure it, so that the use of multiple parallel port,
HDMI_test
- 基于fpga板子和hdmi传输 测试代码文件(hdmi test code for FPGA)
SPI_master
- spi-master模块的verilog(simple program for SPI-Master)
AD9512_coe
- AD9512 提供多路输出时钟分配功能，输入信号最高可达1.6 GHz。它具有低抖动和低相位噪声特性，能够极大地提升数据转换器的时钟性能。(AD9512 provide multiplexed output clock distribution function, the input signal of up to 1.6 GHz.It has a low jitter and low phase noise characteristics, can greatly promote the cl
syn_dp_fifo.v
- 同步双端口FIFO, 可同时读写，FIFO深度宽度可通过参数配置，带SV断言测试。(Dual Port Synchronization FIFO for ASIC/FPGA)
Clock generator
- A clock Generator in verilog