资源列表
mylu
- catapult c任意维矩阵求逆程序，已完成verilog语言转换验证。-catapult c matrix inverse program。
7_lan
- FPGA 网口通信驱动 采用寄存器操作 已经通过验证-FPGA driver for lan port，operating on rejisters，tested successfully
PIC10
- microchip公司PIC16C5X的各个模块的verilog代码，包括代码实现，英文手册和国外参考资料文献-verilog code microchip company PIC16C5X each module, including the code, and foreign reference manuals in English literature
shift_reg
- 移位寄存器，实现了16位移位寄存器的功能，基本原理可以供大家参考-Shift registers to achieve a 16-bit shift register function, the basic principles for your reference
ParallelSerialMult
- 用verilog代码实现了 并行线性序列乘法器，流水线技术实现了乘法操作-Verilog code using a linear sequence of parallel multipliers, pipeline technology to achieve a multiplication operation
gpmc
- GPMC模块源代码。适合初学者的FPGA学习。-GPMC module source code. FPGA for beginners to learn.
pcie_ml555x4_prj
- PCIE的DMA实现，在ML555开发板使用Verilog-PCIE' s DMA implementation using Verilog in the ML555 development board
bram
- Xilinx FPGA内部RAM的使用实验-Xilinx FPGA internal RAM usage experiments
cpld_altera
- DM642核心板采用CPLD扩展地址 CPLD部分程序 可直接烧写-DM642 core board using CPLD CPLD extended address part of the program can be directly programmed
zedboard_CTT_v2013_2_130807
- 在文档里包含有Xilinx公司的软件Vivado的实验教程，可以尽快的对zedboard有个深入的学习了解，有助于初学者的快速学习-In a document containing the Xilinx Vivado experimental tutorial software, you can as soon as possible to have a depth of zedboard learn about, to help beginners learn fast
UVM_TEST
- UVM 的 入门实例，一个完整的能够跑通的实例。其中包括DUT代码，Testbench代码，还有搭建过程说明。很适合用来学习UVM入门。-This paper describes an approach to using Accellera s UVM, the Universal Verification Methodology, for functional verification by mainstream users. The goal is
clock_lcd
- 基于altera FPGA的多功能数字钟程序，但是不是简单的数字钟，还支持VGA图形化钟表显示，并且有鼠标，键盘，温度显示等等功能。-Altera FPGA based multi-functional digital clock program, but not a simple digital clock, timepiece also supports VGA graphics display, and there is a mouse, keyboard, temperature dis