资源列表
sss
- 使用Verilog语言编写源代码.调用一些基本的IP核，如DCM模块、DDS模块ChipScope模块、乘法器模块等来实现调制.最后通过编程并利用FPGA板子实现AM、DBS、SSB的调制。-Using Verilog language source code. Invoke some basic IP cores, such as DCM module, DDS module ChipScope modules, multiplier module to achieve modulation.
9854_VERILOG
- AD9854的FPGA程序，经过试验，全都好使，带有注释，方便开发-The FPGA program AD9854, tested, all so that, with the notes to facilitate the development of
avnet_edk12_4_xbd_files
- 安富利SP605开发板ISE12.4版本的XBD文件，里面包括了开发板所有的接口，包括硬件和软件设计-Avnet SP605 development board ISE12.4 version XBD file, which includes the development board all interfaces, including hardware and software design
LDPC_FPGA
- LDPC码的FPGA实现，大家相互学习下-the code of LDPC implementation by FPGA
cordic_exer
- 自己编写的CORDIC文件，总共6层，收敛于y轴，即求平方根和正切函数-the cordic verilog HDL file made by myself
trafficlight
- VHDL编程的一个交通信号灯，红绿黄灯切换，分主干道支干道，含代码和报告-VHDL programming a traffic lights, red and yellow switch, sub-trunk branch roads, including code and reports
zonghe---20140113
- 本人初学所写，能实现通过串口向FPGA发信号，经由DA产生3种频率的3种波形，另附有仿真波形，FPGA选用EP2C8Q208C8-I wrote a novice can achieve signal to the FPGA via the DA to produce three kinds of wave three kinds of frequencies through the serial port, attached a simulation waveforms, FPGA selec
spdif_verilog
- 数字音频接口spdif ip core，verilog语言编写，带有testbench-spdif verilog ip core
LCD_clock
- FPGA秒表，LCD1602显示,就是简单的有个暂停键，按一下开始再按一下暂停-FPGA stopwatch, LCD display
SPI-Master
- 有关Verilog的SPI通信的代码,可以应用于FPGA的通信-this is verilog code about SPI
adv7123_test
- adv7123的测试源码，Verilog编写，quartus12.1，cyclone测试通过-adv7123 test source code, Verilog prepared, quartus12.1, cyclone test
ADC_Sample
- 本人自己经过实践检验的ADC数据采集程序，通过FPGA采集数据，并用SRAM做缓存，用Verilog编写的，非常好用。-I own proven ADC data collection procedures, data collection through the FPGA and SRAM do with caching, using Verilog prepared, very easy to use.